IHL Kickoff meeting

Friday 17 Jul 2026, 10:00 → 19:20 Europe/Berlin

Room: US-C 109 (Universität Siegen – Unteres Schloss Campus)

Qader Dorosti, Michael Karagounis (FH Dortmund)

🔗 Join Webex Meeting:
https://uni-siegen.webex.com/uni-siegen-en/j.php?MTID=m4148b92d3ba17d835486cc79a0aca976

The Intelligent Hardware Lab (IHL) Kickoff Meeting marks the launch of the IHL within the Cluster of Excellence CmF. The meeting brings together researchers and collaborators to present current activities, identify common research interests, and define the first collaborative projects and technology roadmap of the IHL.

10:00 → 10:30 Registration & Welcome Coffee

10:30 → 11:10 Welcome & Vision

Convener: Qader Dorosti

10:30 Welcome & Introduction

Speaker: Qader Dorosti

10:40 Intelligent Hardware Lab: Vision and Objectives

Speaker: Qader Dorosti

ihl_kickoff_siegen_2026_QDorosti.pdf

11:10 → 12:25 Current Expertise & Capabilities

11:10 Analog & Mixed-Signal ASIC Design

Speaker: Tetsuichi Kishishita

260713_kisisita.pdf

11:20 FPGA Systems & Digital Electronics

Speaker: Michael Karagounis (FH Dortmund)

IHL_Kickoff_FPGA_Digital.pptx

11:30 AI-based Real-Time Waveform Triggering

Speaker: Vesselin Dimitrov

IHL_Dimitrov.pdf

11:40 Cologne Chip: Industrial Partnership and Future Collaboration

Speaker: Michael Gude ((CEO, Cologne Chip AG))

IHL Cologne Chip Industrial Partnership and Future Collaboration 170726.pdf

11:55 Discussion: Existing Expertise and Future Opportunities

12:25 → 13:30 Lunch

13:30 → 15:40 Scientific Drivers & Strategic Partnerships

13:30 eFPGA Technologies: Vision and Opportunities for the IHL

Speaker: Prof. Dirk Koch (Heidelberg University)

Dortmund_IHL.pdf

13:45 EuCAIF: AI for Intelligent Hardware and Scientific Computing

Speaker: Prof. Johan Messchendorp

eucaif_20260717.pdf

14:00 INSIGHT: Detector Electronics Challenges and Opportunities for the IHL

Speakers: Benedikt Otto, Martin Bieker (Helmholtz-Institut für Strahlen- und Kernphysik)

INSIGHT_IHL_Kickoff_Bieker_Otto.pdf

14:15 Edge Computing Architectures and Prospects

Speaker: Dr André Zambanini (Forschungszentrum Jülich)

2026-07-17_Zambanini_Processing_Architectures.pptx

14:30 Towards a readout ASIC for the Lohengrin Experiment

Speaker: Matthias Hamer (Uni Siegen)

LohengrinASIC_IHL.pdf

14:45 DEEP Project: Neural Networks on Hardware

Speaker: Patrick Schwäbig

IHL_Kickoff_ErUM-Data_DEEP.pdf

14:55 Digital Design Infrastructure & Continuous Integration

Speaker: Ilja Bekman (ICA (PGI-4), Forschungszentrum Juelich GmbH)

2026-07-17_Bekman_CmF_CICD_v6.pdf

15:10 Discussion

15:40 → 16:10 Coffee Break

16:10 → 17:35 Building the Intelligent Hardware Lab

16:10 Developing the IHL Infrastructure & Ecosystem

16:25 Technology Vision & Roadmap (ASIC, FPGA, eFPGA & AI Hardware)

16:45 Round Table: Defining the First IHL Activities

17:20 Summary, Action Items & Next Steps

17:30 Closing Remarks