Name: IHL Kickoff meeting
Start: 2026-07-17T10:00:00+02:00
End: 2026-07-17T19:20:00+02:00
Location: Universität Siegen – Unteres Schloss Campus

IHL Kickoff meeting

Friday, 17 July 2026 - 10:00

Monday, 13 July 2026
Tuesday, 14 July 2026
Wednesday, 15 July 2026
Thursday, 16 July 2026
Friday, 17 July 2026

10:00 Registration & Welcome Coffee

10:00 - 10:30
Room: Room: US-C 109
10:30 Welcome & Vision
10:30 - 11:10
Room: Room: US-C 109
Contributions

10:30 Welcome & Introduction - Qader Dorosti

10:40 Intelligent Hardware Lab: Vision and Objectives - Qader Dorosti
11:10 Current Expertise & Capabilities
11:10 - 12:25
Room: Room: US-C 109
Contributions

11:10 Analog & Mixed-Signal ASIC Design - Tetsuichi Kishishita

11:20 FPGA Systems & Digital Electronics - Michael Karagounis (FH Dortmund)

11:30 AI-based Real-Time Waveform Triggering - Vesselin Dimitrov

11:40 Cologne Chip: Industrial Partnership and Future Collaboration - Michael Gude ((CEO, Cologne Chip AG))

11:55 Discussion: Existing Expertise and Future Opportunities
12:25 Lunch

12:25 - 13:30
Room: Room: US-C 109
13:30 Scientific Drivers & Strategic Partnerships
13:30 - 15:40
Room: Room: US-C 109
Contributions

13:30 eFPGA Technologies: Vision and Opportunities for the IHL - Dirk Koch (Heidelberg University)

13:45 EuCAIF: AI for Intelligent Hardware and Scientific Computing - Johan Messchendorp

14:00 INSIGHT: Detector Electronics Challenges and Opportunities for the IHL - Benedikt Otto Martin Bieker (Helmholtz-Institut für Strahlen- und Kernphysik)

14:15 Edge Computing Architectures and Prospects - André Zambanini (Forschungszentrum Jülich)

14:30 Towards a readout ASIC for the Lohengrin Experiment - Matthias Hamer (Uni Siegen)

14:45 DEEP Project: Neural Networks on Hardware - Patrick Schwäbig

14:55 Digital Design Infrastructure & Continuous Integration - Ilja Bekman (ICA (PGI-4), Forschungszentrum Juelich GmbH)

15:10 Discussion
15:40 Coffee Break

15:40 - 16:10
Room: Room: US-C 109
16:10 Building the Intelligent Hardware Lab
16:10 - 17:35
Room: Room: US-C 109
Contributions

16:10 Developing the IHL Infrastructure & Ecosystem

16:25 Technology Vision & Roadmap (ASIC, FPGA, eFPGA & AI Hardware)

16:45 Round Table: Defining the First IHL Activities

17:20 Summary, Action Items & Next Steps

17:30 Closing Remarks

Choose timezone