IHL Kickoff meeting
→
Europe/Berlin
Room: US-C 109 (Universität Siegen – Unteres Schloss Campus)
Room: US-C 109
Universität Siegen – Unteres Schloss Campus
Unteres Schloß 3,
57072 Siegen
Qader Dorosti,
Michael Karagounis
(FH Dortmund)
Description
🔗 Join Webex Meeting:
https://uni-siegen.webex.com/uni-siegen-en/j.php?MTID=m4148b92d3ba17d835486cc79a0aca976
The Intelligent Hardware Lab (IHL) Kickoff Meeting marks the launch of the IHL within the Cluster of Excellence CmF. The meeting brings together researchers and collaborators to present current activities, identify common research interests, and define the first collaborative projects and technology roadmap of the IHL.
Participants
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Registration & Welcome Coffee
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Welcome & VisionConvener: Qader Dorosti
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1
Welcome & IntroductionSpeaker: Qader Dorosti
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2
Intelligent Hardware Lab: Vision and ObjectivesSpeaker: Qader Dorosti
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1
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Current Expertise & Capabilities
- 3
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4
FPGA Systems & Digital ElectronicsSpeaker: Michael Karagounis (FH Dortmund)
- 5
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6
Cologne Chip: Industrial Partnership and Future CollaborationSpeaker: Michael Gude ((CEO, Cologne Chip AG))
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7
Discussion: Existing Expertise and Future Opportunities
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Lunch
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Scientific Drivers & Strategic Partnerships
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8
eFPGA Technologies: Vision and Opportunities for the IHLSpeaker: Prof. Dirk Koch (Heidelberg University)
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9
EuCAIF: AI for Intelligent Hardware and Scientific ComputingSpeaker: Prof. Johan Messchendorp
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10
INSIGHT: Detector Electronics Challenges and Opportunities for the IHLSpeakers: Benedikt Otto, Martin Bieker (Helmholtz-Institut für Strahlen- und Kernphysik)
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11
Edge Computing Architectures and ProspectsSpeaker: Dr André Zambanini (Forschungszentrum Jülich)
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12
Towards a readout ASIC for the Lohengrin ExperimentSpeaker: Matthias Hamer (Uni Siegen)
- 13
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14
Digital Design Infrastructure & Continuous IntegrationSpeaker: Ilja Bekman (ICA (PGI-4), Forschungszentrum Juelich GmbH)
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15
Discussion
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8
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Coffee Break
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Building the Intelligent Hardware Lab
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16
Developing the IHL Infrastructure & Ecosystem
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17
Technology Vision & Roadmap (ASIC, FPGA, eFPGA & AI Hardware)
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18
Round Table: Defining the First IHL Activities
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19
Summary, Action Items & Next Steps
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20
Closing Remarks
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16
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