Login

IHL Kickoff meeting

17 July 2026
Universität Siegen – Unteres Schloss Campus
Europe/Berlin timezone

Contact

Contribution List

26 out of 26 displayed
Export to PDF
  1. 1. Welcome & Introduction
    Qader Dorosti
    17/07/2026, 10:30
  2. 3. Intelligent Hardware Lab: Vision and Objectives
    Qader Dorosti
    17/07/2026, 10:40
  3. 5. Analog & Mixed-Signal ASIC Design
    Tetsuichi Kishishita
    17/07/2026, 11:10
  4. 6. FPGA Systems & Digital Electronics
    Michael Karagounis (FH Dortmund)
    17/07/2026, 11:20
  5. 7. AI-based Real-Time Waveform Triggering
    Vesselin Dimitrov
    17/07/2026, 11:30
  6. 25. Cologne Chip: Industrial Partnership and Future Collaboration
    Michael Gude ((CEO, Cologne Chip AG))
    17/07/2026, 11:40
  7. 10. Discussion: Existing Expertise and Future Opportunities
    17/07/2026, 11:55
  8. 13. eFPGA Technologies: Vision and Opportunities for the IHL
    Prof. Dirk Koch (Heidelberg University)
    17/07/2026, 13:30
  9. 14. EuCAIF: AI for Intelligent Hardware and Scientific Computing
    Prof. Johan Messchendorp
    17/07/2026, 13:45
  10. 11. INSIGHT: Detector Electronics Challenges and Opportunities for the IHL
    Benedikt Otto, Martin Bieker (Helmholtz-Institut für Strahlen- und Kernphysik)
    17/07/2026, 14:00
  11. 23. Edge Computing Architectures and Prospects
    Dr André Zambanini (Forschungszentrum Jülich)
    17/07/2026, 14:15
  12. 15. Towards a readout ASIC for the Lohengrin Experiment
    Matthias Hamer (Uni Siegen)
    17/07/2026, 14:30
  13. 16. DEEP Project: Neural Networks on Hardware
    Patrick Schwäbig
    17/07/2026, 14:45
  14. 26. Digital Design Infrastructure & Continuous Integration
    Ilja Bekman (ICA (PGI-4), Forschungszentrum Juelich GmbH)
    17/07/2026, 14:55
  15. 17. Discussion
    17/07/2026, 15:10
  16. 18. Developing the IHL Infrastructure & Ecosystem
    17/07/2026, 16:10
  17. 19. Technology Vision & Roadmap (ASIC, FPGA, eFPGA & AI Hardware)
    17/07/2026, 16:25
  18. 20. Round Table: Defining the First IHL Activities
    17/07/2026, 16:45
  19. 21. Summary, Action Items & Next Steps
    17/07/2026, 17:20
  20. 22. Closing Remarks
    17/07/2026, 17:30
  21. 9. AI Hardware Validation & Test Infrastructure
  22. 12. Cologne Chip: Industrial Partnership and Future Collaboration
    Dr Michael Gude (CEO, Cologne Chip AG)
  23. 4. Digital ASIC Design within the CmF Cluster
  24. 8. Digital Design Infrastructure & Continuous Integration
    Ilja Bekman (ICA (PGI-4), Forschungszentrum Juelich GmbH)
  25. 24. INSIGHT: Detector Electronics Challenges and Opportunities for the IHL
    Benedikt Otto, Martin Bieker (Helmholtz-Institut für Strahlen- und Kernphysik)
  26. 2. The Intelligent Hardware Lab within the Cluster of Excellence CmF