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    IHL Kickoff meeting

    July 17, 2026
    Universität Siegen – Unteres Schloss Campus
    Europe/Berlin timezone

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    Contribution List

    26 out of 26 displayed
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    1. 1. Welcome & Introduction
      Qader Dorosti
      7/17/26, 10:30 AM
    2. 3. Intelligent Hardware Lab: Vision and Objectives
      Qader Dorosti
      7/17/26, 10:40 AM
    3. 5. Analog & Mixed-Signal ASIC Design
      Tetsuichi Kishishita
      7/17/26, 11:10 AM
    4. 6. FPGA Systems & Digital Electronics
      Michael Karagounis (FH Dortmund)
      7/17/26, 11:20 AM
    5. 7. AI-based Real-Time Waveform Triggering
      Vesselin Dimitrov
      7/17/26, 11:30 AM
    6. 25. Cologne Chip: Industrial Partnership and Future Collaboration
      Michael Gude ((CEO, Cologne Chip AG))
      7/17/26, 11:40 AM
    7. 10. Discussion: Existing Expertise and Future Opportunities
      7/17/26, 11:55 AM
    8. 13. eFPGA Technologies: Vision and Opportunities for the IHL
      Prof. Dirk Koch (Heidelberg University)
      7/17/26, 1:30 PM
    9. 14. EuCAIF: AI for Intelligent Hardware and Scientific Computing
      Prof. Johan Messchendorp
      7/17/26, 1:45 PM
    10. 11. INSIGHT: Detector Electronics Challenges and Opportunities for the IHL
      Benedikt Otto, Martin Bieker (Helmholtz-Institut für Strahlen- und Kernphysik)
      7/17/26, 2:00 PM
    11. 23. Edge Computing Architectures and Prospects
      Dr André Zambanini (Forschungszentrum Jülich)
      7/17/26, 2:15 PM
    12. 15. Towards a readout ASIC for the Lohengrin Experiment
      Matthias Hamer (Uni Siegen)
      7/17/26, 2:30 PM
    13. 16. DEEP Project: Neural Networks on Hardware
      Patrick Schwäbig
      7/17/26, 2:45 PM
    14. 26. Digital Design Infrastructure & Continuous Integration
      Ilja Bekman (ICA (PGI-4), Forschungszentrum Juelich GmbH)
      7/17/26, 2:55 PM
    15. 17. Discussion
      7/17/26, 3:10 PM
    16. 18. Developing the IHL Infrastructure & Ecosystem
      7/17/26, 4:10 PM
    17. 19. Technology Vision & Roadmap (ASIC, FPGA, eFPGA & AI Hardware)
      7/17/26, 4:25 PM
    18. 20. Round Table: Defining the First IHL Activities
      7/17/26, 4:45 PM
    19. 21. Summary, Action Items & Next Steps
      7/17/26, 5:20 PM
    20. 22. Closing Remarks
      7/17/26, 5:30 PM
    21. 9. AI Hardware Validation & Test Infrastructure
    22. 12. Cologne Chip: Industrial Partnership and Future Collaboration
      Dr Michael Gude (CEO, Cologne Chip AG)
    23. 4. Digital ASIC Design within the CmF Cluster
    24. 8. Digital Design Infrastructure & Continuous Integration
      Ilja Bekman (ICA (PGI-4), Forschungszentrum Juelich GmbH)
    25. 24. INSIGHT: Detector Electronics Challenges and Opportunities for the IHL
      Benedikt Otto, Martin Bieker (Helmholtz-Institut für Strahlen- und Kernphysik)
    26. 2. The Intelligent Hardware Lab within the Cluster of Excellence CmF